Pinouts of Connectors

Communication and Networking Riser (CNR) pinout

layout
schematic diagram
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The CNR connector is the interface between the motherboard and the CNR board. The connector provides all of the necessary signals to support several different configurations of audio, modem, and/or LAN subsystems in the system

60 pin CNR bus connector pin-out & layout
60 pin CNR bus connector  at the computer motherboard
The CNR provides support for two different LAN interfaces; an eight-pin interface or a seventeen-pin interface (commonly known as MII or IEEE 802.3u). Support for these two interfaces is provided on two separate CNR connector pin-outs. The pin-out for the eight-pin LAN interface is defined in the Type A CNR connector, while the pin-out for the seventeen-pin LAN interface is defined in the Type B CNR connector.


Type A CNR connector

PinSignalTypeDescription
A1RESERVED-RESERVED
B1RESERVED-RESERVED
A2RESERVED-RESERVED
B2RESERVED-RESERVED
A3GND-Power supply and signal ground return path.
B3RESERVED-RESERVED
A4RESERVED-RESERVED
B4GND-Power supply and signal ground return path.
A5RESERVED-RESERVED
B5RESERVED-RESERVED
A6GND-Power supply and signal ground return path.
B6RESERVED-RESERVED
A7LAN_TXD2INBit 2 (MSB) of the 3-bit data bus transferring data from the MAC to the LAN Interface compliant PLC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
B7GND-Power supply and signal ground return path.
A8LAN_TXD0INBit 0 (LSB) of the 3-bit data bus transferring data from the MAC to the LAN Interface compliant PLC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
B8LAN_TXD1INBit 1 of the 3-bit data bus transferring data from the MAC to the LAN Interface compliant PLC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A9GND-Power supply and signal ground return path.
B9LAN_RSTSYNCOUTThis is a dual function pin that provides either a reset pulse or a synchronization pulse from the MAC to the LAN Interface compliant PLC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A10LAN_CLKOUTData clock from a LAN Interface compliant PLC to the Media Access Controller (MAC). The nominal frequency of this signal determines the data transfer rate between the PLC and the MAC. For detailed information, refer to the current version Core Logic Design Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
B10GND-Power supply and signal ground return path.
A11LAN_RXD1OUTBit 1 of the 3-bit data bus transferring data from the LAN Interface compliant PLC device to the MAC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
B11LAN_RXD2OUTBit 2 (MSB) of the 3-bit data bus transferring data from the LAN Interface compliant PLC to the MAC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A12RESERVED-RESERVED
B12LAN_RXD0OUTBit 0 (LSB) of the 3-bit data bus transferring data from the LAN Interface compliant PLC device to the MAC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A13USB+IN/OUTPositive side of the differential USB 1.x or 2.0 data signal. For more information, refer to the Universal Serial Bus Specification. The state of this signal during reset must meet the Universal Serial Bus Specification.
B13GND-Power supply and signal ground return path.
A14GND-Power supply and signal ground return path.
B14RESERVED-RESERVED
A15USB-IN/OUTNegative side of the differential USB 1.x or 2.0 data signal. For more information, refer to the Universal Serial Bus Specification. The state of this signal during reset must meet the Universal Serial Bus Specification.
B15+5VdualSupplyPositive 5-volt main/standby power supply (can be used for USB power). +5Vdual supply provides full-rated power capacity during working or full-on state, and a limited power capacity during sleep or suspended states. When a +5Vdual supply is not available, this pin must be connected to a +5 volt standby power source. This signal must not be connected to a +5VD, as doing so eliminates the possibility of deep-sleep wake capabilities.
A16+12VSupplyPositive 12-volt main power supply
B16USB_OC#OUTUSB bus over-current signal. For more information, refer to the Universal Serial Bus Specification. The state of this signal during reset must meet the Universal Serial Bus Specification.
A17GND-Power supply and signal ground return path.
B17GND-Power supply and signal ground return path.
A18+3.3VdualSupplyPositive 3.3-volt main/standby power supply. +3.3Vdual supply provides full-rated power capacity during working or full-on state, and a limited power capacity during sleep or suspended states. When +3.3Vdual is not available, this pin must be connected to a +3.3-volt standby power source. This signal must not be connected to a +3.3VD, as doing so eliminates the possibility of deep-sleep wake capabilities.
B18-12VSupplyNegative 12-volt main power supply
A19+5VDSupplyPositive 5-volt main digital power supply
B19+3.3VDSupplyPositive 3.3-volt main digital power supply
A20GND-Power supply and signal ground return path.
B20GND-Power supply and signal ground return path.
A21EE_DININThis signal carries serial data from the core logic MAC Microwire* interface to the Microwire EEPROM (which stores MAC/PLC/PHY specific information) on the CNR board. The EE_DIN signal on the CNR connector must be connected to the DIN pin on the Microwire EEPROM.
B21EE_DOUTOUTThis signal carries serial data from the Microwire EEPROM (which stores MAC/PLC/PHY specific information) on the CNR board to the core logic MAC Microwire* interface. The EE_DOUT signal on the CNR connector must be connected to the DOUT pin on the Microwire EEPROM.
A22EE_CSINThe CNR board uses this signal to enable the serial EEPROM devices on the CNR board. When EE_CS is high (one) the Microwire EEPROM (for the LAN Interface) becomes active. When EE_CS is low (zero) the EEPROM is inactive. The resting state of this signal is low (zero). The state of this signal during reset must be low (zero).
B22EE_SHCLKINThis signal is the serial clock signal from the core logic MAC Microwire* interface to the Microwire EEPROM (which stores MAC/PLC/PHY specific information) on the CNR board.
A23SMB_A1INThis signal is bit 1 of the 3-bit address of the SMBus EEPROM on the CNR board. Refer to Section 6.1.1.2 for detailed information on the connectivity of this signal. The state of this signal during reset must be the SMBus address for the CNR board.
B23GND-Power supply and signal ground return path.
A24SMB_A2INThis signal is bit 2 (MSB) of the 3-bit address of the SMBus EEPROM on the CNR board. Refer to Section 6.1.1.2 for detailed information on the connectivity of this signal. The state of this signal during reset must be the SMBus address for the CNR board.
B24SMB_A0INThis signal is bit 0 (LSB) of the 3-bit address of the SMBus EEPROM on the CNR board. Refer to Section 6.1.1.2 for detailed information on the connectivity of this signal. The state of this signal during reset must be the SMBus address of the CNR board.
A25SMB_SDAIN/OUTBi-directional serial data line between the SMBus master to SMBus slave device(s) on the CNR board. For detailed information on this signal, refer to the current version of the System Management Bus Specification. The reset state of this signal must meet the current version of the System Management Bus Specification.
B25SMB_SCLINSerial clock line from the SMBus master to SMBus slave device(s) on the CNR board. For detailed information on this signal, refer to the current version of the System Management Bus Specification. The reset state of this signal must meet the current version of the System Management Bus Specification.
A26AC97_RESET#INActive low AC TM97 link reset signal. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requirements of the current version of the AC TM97 Component Specification.
B26CDC_DN_ENAB#IN/OUTCDC_DN_ENAB# indicates whether the motherboard or the CNR is in control, or mastering, the AC TM97 interface attached to the CNR Connector. When at a logic low level, the CDC_DN_ENAB# signal indicates that the primary codec on the motherboard is active and controlling the AC TM97 Interface. In addition, the CNR will, when CDC_DN_ENAB# is low, demote its codecs to the next available address and to the next available SDATA_IN signal. See Section 3.3.1 for more details on the implementation of the CDC_DN_ENAB# signal. When at a logic high level, the CDC_DN_ENAB# signal indicates that a primary codec on the CNR is taking control of the AC TM97 Interface. In addition, the motherboard will, when CDC_DN_ENAB# is high, disable all of its codecs. See Section 3.3.1 for more details of how to implement the CDC_DN_ENAB# signal.
A27RESERVED-RESERVED
B27GND-Power supply and signal ground return path.
A28AC97_SDATA_IN1OUTAC TM97 serial data from an AC TM97-compliant codec (primary or secondary) to an AC TM97-compliant Controller. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requirements of the current version of the AC TM97 Component Specification.
B28AC97_SYNCINSynchronization pulse from an AC TM97-compliant controller to all of the AC TM97- compliant codecs on the AC link. This signal is nominally a 1.3 µS wide pulse, which is used to synchronize the AC link. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requirements of the current version of the AC TM97 Component Specification.
A29AC97_SDATA_IN0OUTAC TM97 serial data from a primary AC TM97-compliant codec to an AC TM97-compliant Controller. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requirements of the current version of the AC TM97 Component Specification.
B29AC97_SDATA_OUTINAC TM97 serial data from an AC TM97-compliant controller to all of the AC TM97- compliant codecs on the link. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requirements of the current version of the AC TM97 Component Specification.
A30GND-Power supply and signal ground return path.
B30AC97_BITCLKIN/OUTSerial data clock from primary codec to AC TM97 Controller and any non-primary codecs. The nominal frequency of this signal is 12.288 MHz. For detailed information, refer to the current version of the AC TM97 Component Specification. AC97_BITCLK is an output from a primary codec and an input to non-primary codecs. The reset state of this signal must meet the requirements of the current version of the AC TM97 Component Specification.


Type B CNR connector

PinSignalTypeDescription
A1MII_MDCINManagement data clock signal from Management Data Controller to the MII compliant PHY. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
B1MII_MDIOIN/OUTManagement data input/output signal between the Management Data Controller and the MII compliant PHY. This signal is used to carry bi-directional data for control and status registers. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A2MII_CRSOUTCarrier sense signal from the MII compliant PHY to the MAC. This signal indicates that there is traffic on the LAN wire. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
B2MII_COLOUTCollision detect signal from the MII compliant PHY to the MAC. This signal indicates that a collision has occurred on the LAN wire. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A3GND-Power supply and signal ground return path.
B3MII_TXCOUTData clock from the MAC to the MII compliant PHY. For detailed information, refer to the current version Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A4MII_RXDVOUTReceive data valid signal from the MII compliant PHY to the MAC. This signal indicates that valid data is available on the MII_RXD[3:0] signals. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
B4GND-Power supply and signal ground return path.
A5MII_RXCOUTData clock from a MII Interface compliant PHY to the MAC. For detailed information, refer to the current version Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
B5MII_RXERROUTReceive error signal from the MII compliant PHY to the MAC. This signal indicates that an error has occurred during frame reception. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A6GND-Power supply and signal ground return path.
B6MII_TXD3INBit 3 (MSB) of the 4-bit data bus transferring data from the MAC to the MII compliant PHY. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A7MII_TXD2INBit 2 of the 4-bit data bus transferring data from the MAC to the MII compliant PHY. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
B7GND-Power supply and signal ground return path.
A8MII_TXD0INBit 0 (LSB) of the 4-bit data bus transferring data from the MAC to the MII compliant PHY. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
B8MII_TXD1INBit 1 of the 4-bit data bus transferring data from the MAC to the MII compliant PHY. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A9GND-Power supply and signal ground return path.
B9MII_TXENINTransmit enable signal from the MAC to the MII compliant PHY. This signal indicates that the available on the MII_TXD[3:0] signals can be placed on the LAN wire. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A10RESERVED-RESERVED
B10GND-Power supply and signal ground return path.
A11MII_RXD1OUTBit 1 of the 4-bit data bus transferring data from the MII compliant PHY to the MAC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
B11MII_RXD2OUTBit 2 of the 4-bit data bus transferring data from the MII compliant PHY to the MAC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A12MII_RXD3OUTBit 3 (MSB) of the 4-bit data bus transferring data from the MII compliant PHY to the MAC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
B12MII_RXD0OUTBit 0 (LSB) of the 4-bit data bus transferring data from the MII compliant PHY to the MAC. For detailed information on this signal, refer to the current version of the Core Logic Design Specification and the IEEE 802.3u Specification. The reset state of this signal must meet the requirements set forth in the current version of the Core Logic Design Specification.
A13USB+IN/OUTPositive side of the differential USB 1.x or 2.0 data signal. For more information, refer to the Universal Serial Bus Specification. The state of this signal during reset must meet the Universal Serial Bus Specification.
B13GND-Power supply and signal ground return path.
A14GND-Power supply and signal ground return path.
B14RESERVED-RESERVED
A15USB-IN/OUTNegative side of the differential USB 1.x or 2.0 data signal. For more information, refer to the Universal Serial Bus Specification. The state of this signal during reset must meet the Universal Serial Bus Specification.
B15+5VdualSupplyPositive 5-volt main/standby power supply (can be used for USB power). +5Vdual supply provides full-rated power capacity during working or full-on state, and a limited power capacity during sleep or suspended states. When a +5Vdual supply is not available, this pin must be connected to a +5 volt standby power source. This signal must not be connected to a +5VD, as doing so eliminates the possibility of deep-sleep wake capabilities.
A16+12VSupplyPositive 12-volt main power supply
B16USB_OC#OUTUSB bus over-current signal. For more information, refer to the Universal Serial Bus Specification. The state of this signal during reset must meet the Universal Serial Bus Specification.
A17GND-Power supply and signal ground return path.
B17GND-Power supply and signal ground return path.
A18+3.3VdualSupplyPositive 3.3-volt main/standby power supply. +3.3Vdual supply provides full-rated power capacity during working or full-on state, and a limited power capacity during sleep or suspended states. When +3.3Vdual is not available, this pin must be connected to a +3.3-volt standby power source. This signal must not be connected to a +3.3VD, as doing so eliminates the possibility of deep-sleep wake capabilities.
B18-12VSupplyNegative 12-volt main power supply
A19+5VDSupplyPositive 5-volt main digital power supply
B19+3.3VDSupplyPositive 3.3-volt main digital power supply
A20GND-Power supply and signal ground return path.
B20GND-Power supply and signal ground return path.
A21EE_DININThis signal carries serial data from the core logic MAC Microwire* interface to the Microwire EEPROM (which stores MAC/PLC/PHY specific information) on the CNR board. The EE_DIN signal on the CNR connector must be connected to the DIN pin on the Microwire EEPROM.
B21EE_DOUTOUTThis signal carries serial data from the Microwire EEPROM (which stores MAC/PLC/PHY specific information) on the CNR board to the core logic MAC Microwire* interface. The EE_DOUT signal on the CNR connector must be connected to the DOUT pin on the Microwire EEPROM.
A22EE_CSINThe CNR board uses this signal to enable the serial EEPROM devices on the CNR board. When EE_CS is high (one) the Microwire EEPROM (for the LAN Interface) becomes active. When EE_CS is low (zero) the EEPROM is inactive. The resting state of this signal is low (zero). The state of this signal during reset must be low (zero).
B22EE_SHCLKINThis signal is the serial clock signal from the core logic MAC Microwire* interface to the Microwire EEPROM (which stores MAC/PLC/PHY specific information) on the CNR board.
A23SMB_A1INThis signal is bit 1 of the 3-bit address of the SMBus EEPROM on the CNR board. Refer to Section 6.1.1.2 for detailed information on the connectivity of this signal. The state of this signal during reset must be the SMBus address for the CNR board.
B23GND-Power supply and signal ground return path.
A24SMB_A2INThis signal is bit 2 (MSB) of the 3-bit address of the SMBus EEPROM on the CNR board. Refer to Section 6.1.1.2 for detailed information on the connectivity of this signal. The state of this signal during reset must be the SMBus address for the CNR board.
B24SMB_A0INThis signal is bit 0 (LSB) of the 3-bit address of the SMBus EEPROM on the CNR board. Refer to Section 6.1.1.2 for detailed information on the connectivity of this signal. The state of this signal during reset must be the SMBus address of the CNR board.
A25SMB_SDAIN/OUTBi-directional serial data line between the SMBus master to SMBus slave device(s) on the CNR board. For detailed information on this signal, refer to the current version of the System Management Bus Specification. The reset state of this signal must meet the current version of the System Management Bus Specification.
B25SMB_SCLINSerial clock line from the SMBus master to SMBus slave device(s) on the CNR board. For detailed information on this signal, refer to the current version of the System Management Bus Specification. The reset state of this signal must meet the current version of the System Management Bus Specification.
A26AC97_RESET#INActive low AC TM97 link reset signal. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requirements of the current version of the AC TM97 Component Specification.
B26CDC_DN_ENAB#IN/OUTCDC_DN_ENAB# indicates whether the motherboard or the CNR is in control, or mastering, the AC TM97 interface attached to the CNR Connector. When at a logic low level, the CDC_DN_ENAB# signal indicates that the primary codec on the motherboard is active and controlling the AC TM97 Interface. In addition, the CNR will, when CDC_DN_ENAB# is low, demote its codecs to the next available address and to the next available SDATA_IN signal. See Section 3.3.1 for more details on the implementation of the CDC_DN_ENAB# signal. When at a logic high level, the CDC_DN_ENAB# signal indicates that a primary codec on the CNR is taking control of the AC TM97 Interface. In addition, the motherboard will, when CDC_DN_ENAB# is high, disable all of its codecs. See Section 3.3.1 for more details of how to implement the CDC_DN_ENAB# signal.
A27RESERVED-RESERVED
B27GND-Power supply and signal ground return path.
A28AC97_SDATA_IN1OUTAC TM97 serial data from an AC TM97-compliant codec (primary or secondary) to an AC TM97-compliant Controller. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requirements of the current version of the AC TM97 Component Specification.
B28AC97_SYNCINSynchronization pulse from an AC TM97-compliant controller to all of the AC TM97- compliant codecs on the AC link. This signal is nominally a 1.3 µS wide pulse, which is used to synchronize the AC link. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requirements of the current version of the AC TM97 Component Specification.
A29AC97_SDATA_IN0OUTAC TM97 serial data from a primary AC TM97-compliant codec to an AC TM97-compliant Controller. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requirements of the current version of the AC TM97 Component Specification.
B29AC97_SDATA_OUTINAC TM97 serial data from an AC TM97-compliant controller to all of the AC TM97- compliant codecs on the link. For detailed information, refer to the current version of the AC TM97 Component Specification. The reset state of this signal must meet the requirements of the current version of the AC TM97 Component Specification.
A30GND-Power supply and signal ground return path.
B30AC97_BITCLKIN/OUTSerial data clock from primary codec to AC TM97 Controller and any non-primary codecs. The nominal frequency of this signal is 12.288 MHz. For detailed information, refer to the current version of the AC TM97 Component Specification. AC97_BITCLK is an output from a primary codec and an input to non-primary codecs. The reset state of this signal must meet the requirements of the current version of the AC TM97 Component Specification.

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Source(s): Intel CNR Specification Rev. 1.1, technick.net
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